`timescale 1ns/1ps

module tb_ALU;


// ALU Inputs       
reg   [2:0]  ALU_OP;
reg   [31:0]  A;    
reg   [31:0]  B;    

// ALU Outputs  
wire  [31:0]  F;
wire  ZF;       
wire  OF;       
wire  SF;
wire  PF;
wire  CF;

ALU  u_ALU (
    .ALU_OP                  ( ALU_OP   ),
    .A                       ( A        ),
    .B                       ( B        ),

    .F                       ( F        ),
    .ZF                      ( ZF       ),
    .OF                      ( OF       ),
    .SF                      ( SF       ),
    .PF                      ( PF       ),
    .CF                      ( CF       )
);

integer i;

initial begin
    ALU_OP = 0;
    A = 0;
    B = 0;
    for (i = 0; i < 16; i = i + 1) begin
        #20 ALU_OP = i;
        A = (i % 8 == 7) ?$random()%10 :$random();
        B = $random();
    end
    $write("simulate finished!");
    $stop;
end

endmodule
